Error tolerant sequential circuits



Sept. 15, 1970 1. s. REED ERROR TOLERANT SEQUENTIAL CIRCUITS 4Sheets--She'etv 1 Filed Sept. 5, 1967 Sept 15, 1970 s..REED 3,529,141

ERROR TOLERANT SEQUENTIAL CIRCUITS l Filed sept. s. 1967 4 sheetssheet 2OOOOP v NVENTR.

ZQN 6 5 REED sept. 15, 1970 Filed Sept. 5. 1967 ERROR TOLERANTSEQUENTIAL CIRCUITS l. S. REED 4 Sheets-Sheetl 5 ,QT from/5 v5 Sept. 15,W70 n. s. REED ERROR TOLERANT SEQUENTIAL CIRCUITS Filed Sept. 5, 1967 4Sheets-Sheet I.

United 'States Patent Office 3,529,141 Patented Sept. 15 1970 3,529,141ERROR TOLERANT SEQUENTIAL CIRCUITS Irving S. Reed, Santa Monica, Calif.,assignor to Technology Service Corporation, Santa Monica, Calif., acorporation of California Filed Sept. 5, 1967, Ser. No. 665,524 Int. Cl.Gb 23/02; G06m 3/12 U.S. Cl. 235-153 10 Claims ABSTRACT OF THEDISCLOSURE BACKGROUND OF THE INVENTION The invention generally relatesto binary circuits and more particularly to sequential binary circuitswith error-correcting capabilities.

Since the early stages of the development of digital networks, thedesirability to develop error tolerant networks has been apparent. Theuse of coding theory in such a design has been extensively considered.Examples of binary codes are the Hamming Code, the Reed-Muller Code andothers. One of the primary motivations for the development of errorcorrecting codes, was the need to increase computer reliability.

Since then attempts have been -made to broaden the use of errorcorrecting codes to design a truly errortolerant sequential circuit,i.e. a sequential circuit in 'which one or more logical components orelements may fail anywhere in the circuit without affecting the circuitsdesired output. However most of these attempts have either failed or metwith limited success. Thus a need still exists for a technique -by whicha truly error-tolerant sequential circuit can be designed which utilizeserrorcorrecting codes.

OBJECTS AND SUMMARY OF THE IINVENTION The primary purpose of thisinvention is to provide a novel error-tolerant sequential circuit .basedon a practical design technique.

Another odject of this invention is to provide a sequential circuitwhich is implementable with state of the art techniques and one whichprovides a correct output despite the failure of one or more logicalcomponents therein.

A further object of this invention is to provide a novel sequentialcircuit, whose design and interconnections are based on a new approachto the utilization of coding theory in the design of an error-tolerantsequential circuit.

Still a further object of this invention is to provide a novel binarysequential counter which includes an arrangement to provide a correctmultibit output irrespective of the failure of not more than somepredetermined number of logic elements therein.

Yet another object of this invention is to provide a multibit counterwhich is tolerant to an error in more than one logic element therein.

A further purpose is to provide a novel arrangement in which individualredundant counters are interconnected to provide a counter of increasedbit length which operates correctly despite the failure of any oneelement therein.

These and other objects of the invention are achieved by providing asequential circuit which has the number of data bits necessary to definethe various internal states of the circuit and a number of check orparity bits. For each internal state of the circuit the state of theparity bits is predetermined by a method to be described hereafter indetail. Once the states of the parity bits are determined, the signalsnecessary to sequentially drive both the data bits and check bits fromone internal state to another are derived. The circuit includesredundant logic circuits so that 'when less than some maximum number ofbits or logic circuits fail, a sufficient number of elements or logiccircuits within the sequential circuit contain information from whichthe correct circuit output can be obtained.

To illustrate, consider a 3-bit sequential binary counter, having eightinternal states. For one bit error tolerance, three parity bits arerequired. For each of the eight internal states of the counter, thecorrect value of each parity bit is determined. The counter includesredundant logic circuits so that a correct change in state of either adata or parity bit is achieved. The circuit redundancy is such that itallows for the failure of any one bit or BRIEF DESCRIPTION OF THEDRAWINGS FIG. 1 is a block diagram of one embodiment of a 3-bit counterwith one error tolerance which is in accord With the present invention;

FIG. 2 is the Karnaugh map of lthe internal states of this counterplotted with respect to its three data bits and three parity bits;

FIG. 3 is a partial Karnaugh map of selected states;

FIG. 4 is a diagram of logic elements which can be substituted for themajority elements shown in FIG. 1;

FIG. 5 is another partial Karnaugh map similar to FIG. 3;

FIG. 6 is a block diagram of an embodiment of two 3-bit countersinterconnected to act as a 6-bit counter; and

FIG. 7 comprises a block diagram of a one-bit errortolerant up-down3-bit counter.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Before proceeding to describethe general technique by which error-tolerant sequential circuits aredesigned in accord with the present invention, refer to FIG. 1. Thefigure is a block diagram of one embodiment of a 3-bit binary counterwhich will allow for the correction of one error, i.e. it provides acorrect 3-bit output for each of the counters possible eight internalstates when any one element or circuit therein fails. In FIG. 1 FFA1,FFA2 and FFA3 are three single-input trigger flip-flops corresponding tothose of a conventional 3-bit counter. FFB1, FFB2 and FFB3 are the checkor parity bit flip-flops. The latter ip-ops together with the rest ofthe logic circuits, shown in FIG. 1, serve to provide the countersone-error tolerance. Hereafter, a flip-flop will sometimes be called abistable element.

Each ip-op is triggered or caused to change state by a pulse from ANDgate 12. A ip-iiop changes state from a 1 to 0 or 0 to l when the outputof gate 12 is a pulse. The function of the counter is to sequentiallycount clock pulses C supplied from a source such as clock 14. The outputof clock 14 is connected to one input of each of gates 12 so that one ormore of the ip-flops can be caused to change simultaneously. However, aflip-flop changes state if and only if the change of state signalsupplied at the other input of AND gate 12 is true or 1.

In FIG. 1 a nonprimed output, such as A1, is true or 1 if and only ifthe flip-flop is in state 1. A primed output, such as A1 which denotesnegation, is true or .1 if and only if the ip-op is in state 0. Also inthe gures and G9 denote OR, AND and EXCLUSIVE OR operations,respectively.

As in a conventional 3-bit binary counter, the counter of the presentinvention has the desired successive sequence of states for FFA1, FFA2and FFA3 is shown in the following Table 1.

From Table 1 it is apparent that the change of state signal for FFA1,designated by AA1, is 1 since FFA1 has to change state with each clocksignal or pulse. AA2`=A1 since FFA2 changes state each time FFA1 is instate l or simply 1. Similarly AA3=A1A2 since a change of state occursin FFA3 whenever both A1 and A2 are equal to 51.,9

In order to provide the counter with the one error tolerance the valueof each parity flip-flop is determined for each of the counters eightinternal states S11-S7, shown in Table 1. The values of the data ip-opsA1 and the parity flip-flops B1 at each internal state of the desirederror-tolerant counter are shown in Table 2.

The values of the parity ip-ops or bits (B1) have not been chosenarbitrarily. Rather they are determined systematically from an errorcorrecting code in a manner which is described hereafter in detail. ForTable 2 one can show that the value or state f each of the data ip-ops,i.e., its output may be expressed in terms of the 4 outputs or states ofthe other bits. A1, A2 and A3 may be expressed as follows:

1) A1=2B1=3Bz A2=A1G9B1=A3BB3 A3:A19B2:A25B3 From Equation 1) it is seenthat there are exactly three independent determinations for A1 (=1, 2,3). Define the majority of circuits (2) A1(Mk)=Mk(A1, A299311 A361932)42(Mk) :MaJ-M142, 1419931, A399133) A3(Mk) :Mafiz-l, A199311 A261933)Where and the subscript k indexes the k-th physical realization of thisparticular majority circuit. It should be noted that all the majorityelements of Eq. (2) give the correct outputs if one or less of any ofthe terms A1, A2, A3, B1, B2 and B3 is Wrong.

In the embodiment of the counter shown in FIG. 1 instead of driving gate12 of FFA2 with the output of A2, i.e. instead of AA2=A1, AA2 is givenby AA2=A1 (M1) Where M1 is the first realization of a majority circuitresponding to A1, A261931, A3B2. This circuit is shown in FIG. l. Thegates performing the logic operations A2BB1 and A3B2 are designated bynumerals 16 and 18 respectively.

As previously indicated, the change of state signal for FFA3 isAA3=A1A2. From Table 2 the change of state signals for FFB1, FFB2 andFFB3 may be derived by the standard technique of logical design. Thechange of state equations for the six flip-flops of FIG. 1 aresummarized in the following list:

In accordance with the teachings of the present invention whenever A1has to be employed, the output of a different majority circuit whichresponds to A1, A269131 and 1436932 is employed. Similarly, whenever A1is required the inverted output of a diiferent A1 majority circuit isused. Likewise, instead of A2 the output of a majority circuit isutilized. From the second line of Eq. 2 such a majority circuit respondsto A2, A1BB1 and A3GBB11. In FIG. 1 gates 20 and 22 perform the EX-CLUSIVE OR operations A1BB1 and A3G9B3, respectively.

The change of state equations of Expression 3 may be Written byreplacing A1, A1', A2 and A2 with different realizations of majoritycircuits, so that where M1, M2 etc., are different realizations ofmajority circuits for A1 or A2 as the case may dictate. These majoritycircuits are diagrammed in FIG. 1, together with AND gate 24, which ANDsthe outputs A1 (M2) and A2 (M1) to form AA3. Similarly, inverter 26inverts A1 (M3) to provide AB1, inverters 28, 30 and OR gate 32 are usedto provide AB2 and AB3 is provided by inverter 34 and AND gate-36.

It should be pointed out that the outputs of gates 16 and 18 are used tofeed all the A1 (M1) majority circuits, and similarly the outputs ofgates 20 and 22 feed the different realizations of the A2 (M1) majoritycircuits. By incorporating different realizations of majority circuitsany one majority circuit, the aboVe EXCLUSIVE `OR gates (16, 18, 20, 22)or a ip-op may fail, and yet at least one combination of three elementsand majority circuits is available to reconstruct one of the desiredinternal states of the counter, outlined in Table 1. For example if FFA1fails the true three bit code for each internal state is present at theoutput of any one of A1 (M1) (i=1, 2, 3, 4, 5) and FFA2, FFA3.

Next it should be pointed out that if FFA3 or any one of the circuitsdriving FFA3, e.g. A1 (M2) or A2 (M1), fails an erroneous A3 bit mayresult for the counters third bit. This however is remedied byincorporating in the counter at least one realization of a A3 majoritycircuit, designated in FIG. l as A3 (M1). It operates in accordance withthe third line of expression (2), responding to A3, A1BB1 and A2G9B3.EXCLUSIVE OR gates 38 and 40 perform the operations A1BB1 and A2EBB3,respectively. Thus, the correct third bit of the three bit code ispresent at the output of either FFA3, A1 (M3) or both, for each internalstate.

The foregoing described exemplary embodiment of the invention may besummarized as consisting of a sequential circuit (3-bit counter) withbuilt-in error tolerance (one error). This is realized by incorporatingextra parity bistable elements (B1) and utilizing them together with thedata elements (A1) in redundant logic circuits. These redundant circuitsin turn provide change-of-state signals to the bistable elements toadvance the counter from one internal state to the next. In theforegoing example, majority logic was employed in the redundant logiccircuitry. However such logic technique is presented for explanatorypurposes rather than as a limitation on the teachings of the invention.Other logic techniques may be employed to provide the same desired errortolerance.

This aspect of the invention may best be explained by plotting thecounters various internal states (S-S7) of Table 2 of the Karnaugh map,shown as FIG. 2. Therein the various states S0 through S1 of the counterare plotted.

The circled states C@ represent the desired errorfree states while theuncircled states represent the states with an error in only one of thesix bistable elements, A1, A2, A3, B1, B2 and B3. The empty states aredont care states of the map. Such a map can be utilized to determine thelogic circuits for the required change-ofstate signals. The use of aKarnaugh map for logic design is well known in the art.

From Table 2 it is seen that A2 changes state to a succeeding state whenthe counter is in any one of states S1, S3, S5 and S1. Thus the map ofFIG. 2 is utilized by considering only these four plotted states toderive the logic for AA2. Such use is diagrammed in FIG. 3 wherein onlystates S1, S3, S5 and S, are plotted. Zone Z1 may be expressed asA1-A3B2. Similarly, zones Z3 through Z8 are represented by A1A2B1,A1A2B1,

Az'Aa'BfBz', A2A3"B1"B2 A2"A2"B1'B2, A2"A3"B1'B2 and A2,'A3'B1B2,respectively. The join of all zones covers the map of FIG. 3 for AA2.Thus It can easily be shown that the output of OR gate 50 is the same asthat of majority circuit A1 (M1) (FIG. 1) used to provide the change ofstate signal for FFA2 when majority logic is employed. This can best bedemonstrated by expanding the operation of A1 (M1) and then defining thezones on the Karnaugh map which are included therein.

A1(M1)=M1(A1,2B11A3BB2) (A261931) (1439932) |A1(A3@B2) +A1(2G9B1) InFIG. 5 zone Zla denes the function (A2BB1) (A369122), while zone Z2adefine the function A1 (A3GB2). Function A1 (A2G9B1) is defined by zoneZ311. By comparing the maps of FIGS. 3 and 5, it is clearly seen thatthe identical zone pattern is defined in each of them. Thus it should beappreciated that the same change-of-state signal is supplied to FFA2when majority logic is employed as shown in FIG. 1 or when the signal isprovided by the logic arrangement shown in FIG. 4. The map of FIG. 2 maybe similarly utilized to derive the logic necessary to generate thechange-of-state signals for the other bistable elements, i.e. FFA3, FFB1FFB2, FFB3. As seen from Table 2 state S3 and S7 need be considered forAA3, while states S0, S2, S1 and S6 are required for AB1. Similarly, forAB2 states ,80, S1, S2, S4, S5 and S6 need be considered and for AB3only states S1 and S5 are of importance. The logic equations which couldbe so derived are summarized below:

Just as the logic arrangement of FIG. 4 is yused to implement AA2=01,similar logic arrangements, employing a plurality of AND gates Whoseoutputs are fed t0 OR gates, are utilized to implement the otherEquations 7.

The foregoing comprises the description of two embodiments of a 3-bitcounter with one error tolerance. In one embodiment majority logic isemployed While in the other embodiment a different logic arrangement isutilized. Either embodiment is of an up counter since each clock signalincreases the counters binary count by one as seen from the binarynumbers represented by A1, A2 and A3 in Tables 1 and 2.

If desired the bit capacity of the up counter may be increase by addingadditional data and parity bits. FIG. 6 is a block diagram of a six bitup counter with one error tolerance. It consists of the previouslydescribed three data bits FFA1 FFA2 FFA3, the three parity bits FFB1FFB2 FFB3 and three additional data bits FFA4 FFA5 FFA5 as Well as threeadditional parity bits FFB4 FFB5 and FFBG.

The change of state signals for the ip-iiops are as follows:

where a1, u2, 131, [32 and ,B3 are dened by Equations 7. a3, a4, 184,,85 and [36 are the same as a1, a2, B1, [32 and ,B3 respectively with A1A2 A3 B1 B2 and B3 and their complements replaced by A4 A5 A6 B4 B5 andB6 in succession. that is,

In Equations 8 S7(R1) (i: l, 2, 3, 4, 5, 6) denote distinct physicalrealization of S7 (Redundant) which is derivable from the Karnaugh mapshown in FIG. 2.

The foregoing expression for S7 (Redundant) may be implemented by alogic circuit consisting of three fourinput AND gates which are fed toa1 three-input OR gate. Six distinct physical realizations of S7 arerequired for complete one-error toleration, i.e. six identical logiccrcuits for S7 (Redundant) are needed. The counter of FIG. 6 can bethought of as consisting of two 3-bit counters with one error tolerancewhich are connected together in such a. way that the total circuit isone-error tolerant. The counters are designated C1 and C2. The change ofstate signals for the bits of counter C1 are a function of only thestates or values of the of the bits of C1. However, the change of statesignals for the bits of `C2 ade dependent on the states or values of thebits of both counters. Similarly, more than two 3-bit one error tolerantcounters may be coupled to obtain a counter of 3n bits which is oneerror tolerant, and wherein n is an integer.

The teachings of the invention can be employed also to devise anerror-tolerant up-down counter. Such a counter utilizes additional logiccircuits and input control signals. An arrangement for this circuit isshown in FIG. 7. This diagram displays a complete block diagram of athree bit up-down counter with one error tolerance which employsmajority logic. In FIG. 7 elements like those shown in FIG. l aredesignated by like numerals.

The change of state equations for the up-down counter are as follows:

In the foregoing relationships U is 1 for counting up and D is l forcounting down. As seen from FIG. 7, the counter includes a up-downcontrol unit 52 which provides a 1 output on a line U to count up and a1 on a line D to count down. These lines are fed to OR gate 54 whichprovides a 1 output if either U or D is 1.

The AA2 term is provided by the majority circuit A1 (M1) together withinverter 56, AND gates 57 and 58 and OR gate 60. Gates 57 and 58 producethe terms UA1(M1) and DA1(M1) respectively. These are fed to OR gate 60.Inverters 62 and 63 and gates 64 and 65 are added to circuits A1(M2),A2(M) and gate 24 to implement AAS, while AB1 is implemented by A1(M3)inverter 26 together with gates 67, 68 and 69. AND gates 71 and 72 andOR gates 73 and 74 are added to implement AB2 while an inverter 75, ANDgates 76 and 77 and an OR gate 78 are added to implement AB3.

Accordingly there has been shown and described herein a novel sequentialcircuit, which has been made errortolerant, by the addition of paritybits and redundant logic circuits. For each internal state of thecircuit a fixed preselected state relationship exists for the paritybits (B1). The outputs of the parity bits and the circuits data bits(A1) are utilized in redundant logic circuitry to provide each bit witha change of state signal. By employing the redundancy of logic any onebit or bistable element or any one logic circuit, either a majoritycircuit or gate, may fail. However, despite such failures a suicientnurnber of bistable elements and logic circuits are contained in thesequential circuit to provide the correct binary code for each internalstate.

Therefore, the invention has been described in conjunction with specificembodiments of a 3-bit binary counter with one error tolerance. Theprocess used to derive the values of the parity bits (B1) for each ofthe counters eight interval states as outlined in Table 2, and thechange-of-state equations can be used to design any elementarysequential binary circuit with any desired error tolerance. It is thepurpose of the following description to illumine this process in Iallits generality. The steps of this process are as follows:

Step 1 qn-k (1n-kn: 0 0 1 (1X) The coded words for states S0, S1 Sm 1compose the set V of all v such that vHT=0 (2x) where V=(A1, A2 Ak B1,B2 Bxl-k) is a row vector of the internal state bits A1, A2 Ak andauxiliary bits B1, B2 Bn k and T denotes matrix transpose. By Eq. (2x),bits B1 are determined by k Bi=2qiAi=llliAiq2iAzB qkik for i=1, 2 n-k,and where the sun symbol G9 denotes snm modulo two or the exclusive oroperation.

Step 3 Replace states S1 by states S1* in such a way that if SJ-corresponds to A10), A20) AkU'), that S5* corresponds to A10), A20)A110), B10) Bn k0), where A10)=0 or l and B10) is determined by Eq.(3x).

Designate flip-flops B1 as auxiliary bits. Determine the change ordriving circuits for the B1 in terms of bits Aj (j=l, 2 k) and otherinput variables, thereby completing the logical design of the sequentialcircuit with states Sj* replacing Sj for j=0, 1, 2 m-l.

9 Step 4 Since an element v of code V is orthogonal to any row of H, vis orthogonal to every element of V.L, where V.L is the vector spa-cegenerated by the rows of H; i.e. if v is in V and u is in VJ., thenvuT=0. V.L is the dual code of V. Consider any uu) in V.L such that theA, component Aj(1)|=1, i.e.

un =(A1u 12(1) Ain) I Aka)y Blu) ,Bgld where A10) and Bju) are either `0or l. Since vu(1)1l=0,

where v=(A1, A2 Ak, B1 Bn k), we may solve Similarly, nd um) such thatu(2)u(1) and A, 2).=1, 14(3) such that uiauuu) and Aj(3)|=1, and ingeneral 140') such that wmemn# 14(1) and Aj(f)l=1. In this way A, isdetermined at most 2(11-1-1) times by the equations for r=1, 2 2(1`1)and j=l, 2 k, where denotes the sum, modulo with the jth term skipped.From this set of determinations for Aj, find that subset S of V.L fromwhich a set lof equations of type (4x) can be derived with the leastoverlap (or are closest to twostep orthogonality), and such that amajority test of the determinations allows for at least d-errors where dis the number of errors the code will correct. If the number of ones inany row of H is exactly three, then the codes are modified first-orderReed Muller Cod'es, and the set S of least overlap is easily computed.

Implement physically all possible parity equations of type (4x)generated by the set S for each Aj (j=1, 2 k).

Step 5 Consider a driving equation for either ilipdlop A, or Bj asdetermined by Step 3. This will :be either one or two functions of form(A1,A2 Ak, C1, C2 Cr) of the original internal state variables A1 Ak andinput variables C1, C2 Cr. For Aj substitute where A(0)=Aj and AJ-(r)are given by Eq. (4X) for (j=1, 2 k),

is the first majority circuit used for Aj (the sum in Eq. (5X) is theordinary arithmetic sum) and n1 is the number of vectors in S such thatAj=1. Substitute AJ-(l) for Aj in f(A1 Ak, C C) only if f is an explicitfunction of Aj.

For the driving equations for each flip-flop of set A1, A2 Ak, B1, yB2i. Bn k repeat the above process but never use the same majority circuitfor the driving equations of derent ilip-ops. Denote the kth physicallyrealized majority circuit for variable Aj by Always utilize a majoritycircuit for a primary internal state variable AJ- in a flip-flop channelwhich is separate and distinct from those majority circuits for Aj inother flip-Hop channels.

The above sequence of steps makes possi'ble the failure of one or morecircuits in d or less flip-flopchannels. In spite of the failure ofthese ip-op channels, the sequential circuit will continue to operatesatisfactorily and produce correct outputs by Iway of further majorityelements or decoding circuits.

It should be appreciated that those familiar with the art may makemodications and/or substitute equivalents in the arrangement as shownwihtout departing from the spirit of the invention. It should further beappreciated that error-indicating circuits and means may be added to anyone of the foregoing described embodiments to indicate the presence ofan eiror in any of the flip-flops or the logic circuits. These circuitsand means may take the form of lights, alarms, etc. Therefore, all suchadditions, modications and/ or equivalents are deemed to fall within thescope of the invention as claimed in the appended claims.

What is claimed is:

1. An error-tolerant binary circuit comprising:

K bistable data elements, each data element 'being drivable from onestable state to the other, an element in one stable state providing anoutput representative of the digit, one, and the other stable stateproviding an output representative of the digit, zero;

a plurality of bistable check elements, each check element beingdrivable from one stable state to the other, a check element in onesta'ble state providing an output representative of the digit, one, andthe other stable state providing an output representative of the digit,zero;

first logic means to which outputs of said data element and said checkelements are supplied for providing control signals representative ofthe relationship of.

the states of the bistable elements, supplying said outputs;

second logic means for utilizing said control signals and the outputs ofthe K data elements for providing each of the data and check elementswith a separate change of state signal;

a source of clock signals;

a separate bistable element control means coupled to each bistableelement;

rst connecting means supplying each control means with the change ofstate signal of the bistable element associated therewith; and

second connecting means for simultaneously supplying all the controlmeans with clock signals from said source, whereby a ybistable elementchanges from one state to the other in response to the clock signal ifand only if the change of state signal supplied to the control meansthereof is of a predetermined value, said binary circuit including asufficient number of logic means so that each of the circuits internalstates is accurately definable therein even when d bistable elements andlogic means fail, d being not greater than a predetermined number.

2. A sequential binary counter for providing an accurate binary count ofclock signals supplied thereto irrespective of failure of not more thand elements therein comprising:

K bistable data elements each drivable from one stable state in whichthe element output represents the digit, one, to the other stable statein which the element output represents the digit, zero;

a plurality of bistable check elements each drivable from one stablestate in which the element output represents the digit, one, to theother stable state in which the element output represents the digit,zero, the number of check elements being a function of k and d;

a rst plurality of logic-performing elements each responsive to theoutputs of at least two of said bistable elements to provide an outputwhich is in a first state 1 1 when the outputs supplied to the elementare in a preselected relationship and in a second state when the outputssupplied to the element are in a different than said preselectedrelationship;

a second plurality of logic-performing elements coupled to said bistabledata and check elements and to said rst plurality of logic elements forproviding a different change of state signal for each bistable element,the level of each change of state signal being a function .of theoutputs of a physically distinct group of logic performing elements insaid first plurality; and

a source of clock signals for simultaneously providing clock signals tosaid data and check elements to simultaneously change the states of allbistable data elements whose change of state signals are of apredetermined level.

3. The counter as recited in claim 2 wherein said second plurality oflogic-performing elements includes separate distinct logic-performingelements for providing each of said change of state signals, wherebyfailure of any one of the logic-performing elements in said secondplurality does not aiect the accurate performance of elements performingan identical logic operation.

4. The counter as recited in claim 3 wherein each logicperformingelement in said rst plurality is an EXCLU- SIVE OR gate for performingthe EXCLUSIVE OR operation on at least the outputs of two of saidbistable elements, and said second plurality of logic-performingelements includes majority elements responsive to the outputs of atleast two EXCLUSIVE OR gates and the output of one data element.

5. The counter as recited in claim 4 wherein k=3, d=l, said counterincluding three check bits FFB1, FFBZ and FFB3, said first plurality oflogic-performing elements including liirst, second, third and fourthtwo-input EX- CLUSIVE OR gates performing respectively the operationsA2BB1, A369132, AlGBl and A3BB3, where A1, A2 A3 are the respectiveoutputs of three data elements FFA1, FFA2 and FFA3, the A1 output beingthe least significant bit, and said second plurality of logic performingelements includes live physically distinct majority circuits eachresponding to the output of FFAI, and the iirst and second EXCLUSIVE ORgates, said second plurality of logicperforming elements furtherincluding three physically distinct majority circuits each responding tothe outputs of FFA2 and the third and fourth EXCLUSIVE OR gates.

6. The counter as recited in claim 3 wherein k=3 comprising elementsFFA1, FFA2, FFAa, d=1 and said plurality of check elements includesthree elements FFBI, FFB2 and FFB3, and said iirst and secondpluralities of logic-performing elements include physically distinct ANDgates and live OR gates to provide change of state signals (Z1, (12, l,z and 3 for element FFA2, FFA3, FFBl, and FFB3 respectively, where al,a2, l, ,32 and ,B3 are defined by equations (7). a3, a4, 184, /35 and,S6 are the same as a1, a2, ,81, [32 and ,B3 respectively with A1 A2 A3B1 B2 and B3 and their complements are replaced by A4 A5 A6, B4, B5 andB6 in succession. That is and where S7(Ri) (==1, 2, 3, 4, 5, 6) denotedistinct physical realizations of S7 (Redundant) where i 8. A sequentialcircuit for providing an error-free binary output which is a function ofthe binary state of at least one of k bista'ble data elements thereof,irrespective of malfunctioning of not more than d elements or logicmeans therein comprising:

k bistable data elements; y bistable check elements, y being a functionof d and k;

means responsive to clock signals to enable the simultaneous change ofthe state of each of said k and y bistable elements; and

Redundant logic means responsive to the states of said k data elementsand said y check elements for providing each bistable element with achange of state signal;

means for providing clock signals; and

k and y control means simultaneously responsive to each clock signal,each control means being associated with a diierent bistable element tochange the state of the element in response to the clock signal if andonly if the change of state signal of the element is of a selectedvalue, whereby for each preselected state relationship of the k dataelements with which a predetermined state relationship of the y checkelements is associated, said circuit includes, among said elements andlogic means, a suicient number of elements and logic means which are insaid preselected state relationship, despite malfunctioning of not morethan d elements and logic means therein.

9. The sequential circuit as recited in claim 8 wherein said circuit isa k bit counter, sequentially operable to define 2k state relationshipsfor said k data elements, with predetermined states for said y checkelements associated with each of said 2k states, said circuit includingfor each of said 2k state relationships at least one group of k elementsand logic means whose states are in the desired relationshipirrespective of the malfunctionlving of not more than d elements andlogic means therein.

10. The sequential circuit as recited in claim 9 further including meansresponsive to an up input control signal supplied thereto tosequentially change the state rela- 13 tionship of said k data elementsfrom one state to a different state which represents a greater by onebinary number, said means being further responsive to a down inputcontrol signal to control the change of states of the k data elements torepresent a smaller by one binary number.

References Cited Logic Redundancy Improves Digital System Reliability.In NASA Tech Brief, 65-10025, February 1965.

14 Goldberg, I. Simplified Circuit Corrects Faults in Parallel BinaryAInformation Channels. In NASA Tech Brief, 66-10261, June 1966.

EUGENE G. BOTZ, Primary Examiner R. S. DlLDINE, IR., Assistant ExaminerU.S. Cl. X.R.

